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Technical Sharing | Application of Network Analysis Time-Domain Mode in RF Switch Chip Testing
2026-06-18
RF switch chips are critical components in wireless communication systems. From the RF front-end of mobile phones to base station antenna arrays, The performance of switches directly affects signal integrity and the overall power consumption of the system. During mass‑production testing, engineers must verify insertion loss, isolation, and—most critically—the switching time, which determines how long it takes for the switch to transition from one state to another and directly affects the system’s response speed.
For a long time, the industry has commonly relied on vector signal transceivers (VSTs) to perform RF switch testing. The VST excites the switch’s common port with a continuous-wave signal and then captures the output‑side signal variations at the throw‑end, from which it extracts the switching transient. This approach is well‑established and reliable, but… When dealing with multi‑throw terminal switches, an external switch matrix is required to expand the number of channels; this not only results in a complex system architecture but also drives up hardware costs. 。

System block diagram of the VST test switch chip
Meanwhile, Semi-mile is self-developed PXI vector network analyzer, the SNA3308, The network partitioning time-domain approach offers a new perspective for this scenario. : Allow the network analyzer to stop sweeping and instead remain fixed at a single frequency point, Directly “view” the variation of signal amplitude over time. 。

Semi-mile’s self-developed PXI network analyzer, the SNA3308.
The Core Principle of the Network Partitioning Time-Domain Mode
The standard application of a vector network analyzer is swept‑frequency measurement: the signal source steps or scans across a frequency range, while the receiver synchronously acquires the response at each frequency point, ultimately yielding a characteristic curve that plots the magnitude and phase of the signal ratio as a function of frequency. From a hardware‑architecture perspective, however, the vector network analyzer also possesses another intrinsic capability: Its highly stable RF signal source can lock onto a single frequency, generating a pure single-tone continuous wave; the wideband receiver, paired with a high-speed ADC, enables continuous acquisition of signal amplitude variations with extremely high temporal resolution.
Time-domain mode leverages this very characteristic: the instrument forgoes frequency sweeping, with the signal source continuously transmitting a single‑frequency continuous wave, while the receiver performs continuous sampling to directly acquire the time‑domain waveform of the voltage amplitude at the receive port. In this configuration, the horizontal axis of the display is replaced by time, and the vertical axis corresponds to the measured signal level, transforming the instrument from a frequency‑domain analyzer into a time‑domain test tool specialized for capturing signal transitions along the RF path.
This characteristic is highly aligned with the testing requirements of RF switches. The essence of switch toggling is the transition of the signal in the RF path from one steady state to another. . Network segmentation The time-domain mode can fully capture this transient process with high temporal resolution. , and leveraging the inherent amplitude measurement accuracy of the network‑segmentation system, it can also Ensure the accuracy and reliability of subsequent parameter extraction results. 。
Switching Time Measurement: Taking MIPI Control as an Example
RF switches feature a variety of control interfaces, with GPIO and MIPI being two common methods. Here, we use an MIPI‑controlled switch as an example to illustrate the measurement procedure.
During testing, one port of the SNA3308 is connected to the switch’s common terminal and a continuous-wave signal is applied, while the remaining ports are individually connected to the respective throw terminals. The industry provides a precise definition of switching time: it is the interval measured from the last falling edge of the MIPI CLK signal to the moment when the RF signal amplitude rises to 90% of its steady-state value. The reason for latching on CLK rather than DATA is that the voltage level of the DATA signal at its trailing edge depends on the specific instruction content and does not always remain high. In contrast, the last falling edge of CLK exhibits stable timing, making it an ideal time reference point.

When observing MIPI triggering and switching on an oscilloscope
The instrument’s trigger system locks onto the last falling edge of the MIPI CLK as the time reference, enabling all receive channels to simultaneously initiate high-speed data acquisition. The FPGA performs real-time processing on the acquired data: first, it computes the final amplitude reference based on the steady-state sampling data, and then it searches along the time axis for the moment when the amplitude first reaches 90% of the reference value. The time difference between this reference point and the 90% amplitude point is the switching time of the path under test.

Switching Power Fluctuation Line Chart
Taking a single-pole double-throw switch as an example, the four ports of the SNA3308 precisely correspond to the common terminal and the two throw terminals. Upon receiving a switching command, one throw terminal becomes conductive, causing the signal amplitude to rise, while the other throw terminal is turned off, resulting in a drop in signal amplitude. Under a multi‑port parallel acquisition architecture, the SNA3308 simultaneously measures the rise time of the on‑state path while naturally capturing the fall behavior of the off‑state path. A single trigger is sufficient to fully record the switching transient at both ports, and it concurrently provides parameters such as switching time, insertion loss, and isolation. 。
For multi‑throw terminal switches, an external switch matrix can be connected to expand the test channels; meanwhile, most conventional switches require no additional peripherals and can be tested directly upon connection, significantly reducing system integration complexity.

SNA3308 External Matrix Test System
The Unique Value of the Network-Splitting Time-Domain Mode
Use the network analyzer for time-domain testing, Value is reflected in:
1. Directness of the measurement link The receiver directly detects variations in the RF signal amplitude, with a short signal path and few intermediate stages, thereby effectively reducing sources of error.
2. The device boasts excellent amplitude measurement accuracy. It should be noted that switch‑time measurements are based on changes in the relative signal amplitude, with the 90%‑amplitude point determined through normalization using the steady‑state value; thus, they are not highly dependent on the system’s absolute power accuracy. Network analyzers require only scalar calibration, which can compensate for amplitude deviations introduced by cables and connectors, providing a consistent measurement reference across all channels. Such calibration procedures are straightforward and sufficiently meet the requirements of time‑domain amplitude measurements.
3. A single PXI vector network analyzer module, paired with an embedded controller, can form a standalone test station, resulting in a streamlined system that is highly convenient for routine calibration and maintenance. When multiple stations operate in parallel, each chassis is deployed independently without interfering with one another, offering excellent scalability and manageability.
The network‑analysis time‑domain mode does not seek to replace VST’s communication‑testing capabilities, It simply offers a choice that aligns more closely with the essence of measurement, specifically within the niche application of RF switch‑chip testing. Leveraging the vector network analyzer’s core advantage in amplitude measurement, it captures the fine details of every state transition along the switching path, enabling more intuitive and precise characterization of switching times.
This is precisely the core design philosophy behind Semi-mile’s self-developed SNA3308: pairing dedicated hardware with tailored test scenarios to maximize instrument performance.